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From: [e-mail] (Michael Altarriba)
Subject: comp.lsi.cad Frequently Asked Questions With Answers (Part 1/4) [LONG]
Message-ID: <lsi-cad-faq/[e-mail]>
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Summary: This is a biweekly posting of frequently asked questions with answers
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Archive-name: lsi-cad-faq/part1


Welcome to comp.lsi.cad / comp.lsi: this is the biweekly posting of fre-
quently asked questions with answers.  Before you post a question such as
"Where can I ftp spice from?", please make sure that the answer is not
already here.  If you spot an error, or if there is any information that
you think should be included, please send us a note at
[e-mail].

The products and packages described here are intended for research and edu-
cational use. As such, we try to limit our entries to applications which
are available for free or at low cost (< $500). We also wish to limit the
descriptions to at most a page (60 lines) in length.

    Bret Rothenberg <[e-mail]>
    Wes Hardaker <[e-mail]>
    Mike Altarriba <[e-mail]>

    Solid State Circuits Research Laboratory
    Electrical Engineering and Computer Science
    University of California, Davis
    Davis, California 95616

----------------------------------------------------------------------

  $Id: comp.lsi.cad.FAQ.ms,v 1.62 93/08/20 16:00:38 altarrib Exp $

  Frequently Asked Questions with Answers

    1: Readership report for comp.lsi.cad and comp.lsi
    2: Mosis Users' Group (MUG)
    3: Improved spice listing from magic.
    4: Tips and tricks for magic (Version 6.3)
    5: What can I use to do good plots from magic/CIF?
    6: What tools are used to layout verification?
    7: EDIF data exchange format.
    8: What layout examples are available?
    9: How can I get my lsi design fabbed and how much will it cost?
    10: Mosis fabrication services.
    11: Archive sites for comp.lsi.cad and comp.lsi
    12: Other newsgroups that relate to comp.lsi*
    13: Simulation programs tips/tricks/bugs
  ! 14: Getting the latest version of the FAQ
    15: Converting from/to GDSII/CIF/Magic
    16: CFI (CAD Framework Initiative Inc.)
    17: What synthesis systems are there?
    18: What free tools are there available, and what can they do?
    19: What Berkeley Tools are available for anonymous ftp?
    20: What Berkeley Tools are available through ILP?
    21: Berkeley Spice (Current version 3f2)
    22: Octtools (Current version 5.1)
    23: Ptolemy (Current version 0.4)
    24: Lager (Current version 4.0)
    25: BLIS (Current version 2.0)
    26: COSMOS and BDD
    27: ITEM
    28: PADS logic/PADS PCB
    29: Another PCB Layout Package
    30: Magic (Current version 6.3)
    31: PSpice
    32: Esim
    33: Isplice3 (Current version 2.0)
    34: Watand
    35: Caltech VLSI CAD Tools
    36: Switcap2 (Current version 1.1)
    37: Test Software based on Abramovici text
    38: Atlanta and Soprano automatic test generators
    39: Olympus Synthesis System
    40: OASIS logic synthesis
    41: T-SpiceTM (was CAzM), a Spice-like table-based analog circuit simulator
    42: Galaxy CAD, integrated environment for digital design for Macintosh
    43: Gabriel DSP development system
    44: WireC graphical/procedural system for schematic information
    45: LateX circuit symbols for schematic generation
    46: Tanner Research Tools (Ledit and LVS) (Commercial Product)
    47: SIMIC, a full-featured logic verification simulator
    48: LASI CAD System, IC and device layout for IBM compatibles
    49: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles
    50: MagiCAD, GaAs Gate Array Design through MOSIS
    51: XSPICE, extended version of Spice
    52: MISIM, a model-independent circuit simulation tool
    53: Nelsis Cad Framework
    54: APLAC, a system-level simulator and IEEE-488 measurement tool
    55: SLS, a switch-level simulator
    56: OCEAN, a sea-of-gates design system
  + : new item
  ! : changed
  ? : additional information for this subject would be appreciated.

1: Readership report for comp.lsi.cad and comp.lsi

  This is the full set of data from the USENET readership report for Jul
  93.  Explanations of the figures are in a companion posting in
  news.lists.

          +-- Estimated total number of people who read the group,
          |   worldwide.
          |      +-- Actual number of readers in sampled population.
          |      |     +-- Propagation: how many sites receive this group
          |      |     |   at all.
          |      |     |      +-- Recent traffic (messages per month).
          |      |     |      |     +-- Recent traffic (kilobytes per
          |      |     |      |     |   month).
          |      |     |      |     |       +-- Crossposting percentage
          |      |     |      |     |       |    +-- Cost ratio:
          |      |     |      |     |       |    |   $US/month/rdr
          |      |     |      |     |       |    |      +-- Share: % of
          |      |     |      |     |       |    |      |   newsreaders
          |      |     |      |     |       |    |      |   who read this
          |      |     |      |     |       |    |      |   group.
          V      V     V      V     V       V    V      V

   547  37000   604   82%    58   244.4    27%  0.01   1.6%  comp.lsi
   438  41000   674   78%    65   122.1     7%  0.00   1.7%  comp.lsi.cad

2: Mosis Users' Group (MUG)

  (From the Microelectronics Systems Newsletter)

  The MOSIS  Users'  Group (MUG)  Newsletter is now known as the Microelec-
  tronic Systems Newsletter.  The name change reflects the increased scope
  of this newsletter which includes not only items of interest to those
  designing integrated circuits for prototyping via MOSIS but also for
  those designing, prototyping and producing microelec- tronic systems.
  This issue is being distributed only via elec- tronic means to about 1600
  individuals throughout the world.

  We hope that you enjoy receiving this newsletter and find it useful.
  Comments and suggestions should be directed to the Editor along with any
  change in address. If you prefer not to receive messages of this type,
  which will occur no more often than monthly, please contact the Editor.

          Newsletter Editor
          Prof. Don Bouldin
          Electrical & Computer Engineering
          University of Tennessee
          Knoxville, TN 37996-2100
          Tel:  [phone]
          FAX:  [phone]
          Email:  [e-mail]
          Compmail II:  D.Bouldin

  A variety of design files and CAD tools contributed by the members of the
  MOSIS Users' Group (MUG) are now available via anonymous ftp from
  "venera.isi.edu" (128.9.0.32) in directory "pub/mug".  The files "readme"
  and "index" should be retrieved first.  These files are provided "as is",
  but may prove very helpful to those using the MOSIS integrated circuit
  prototyping service.

3: Improved spice listing from magic.

  Hierarchical extractions with net names: ext2spice done by Andy Burstein
  <[e-mail]>:

  This program will do hierarchial extraction using node names.  It sup-
  ports PS, PD, AS, and AD extraction as well.  It is available for ftp
  from ic.berkeley.edu in pub/spice3/ext2spice.tar.

  Poly and well resistance extraction: There are persistent rumors that
  people have this working, however, all I have seen is extracted poly
  resistor with each end shorted together, ie each end has the same node
  name/number.

  (This is the most annoying problem that I typically encounter daily.  If
  ANYONE knows a fix for this, please tell us! I wrote a real quick and
  dirty set of scripts/programs to edit the magic file.  It will break the
  poly contacts and relabel them.  This is a real hack, but all other solu-
  tions require modification of the magic code itself.  This procedure only
  works with an extractor that handles labeled nodes, i.e. ext2spice from
  above.  --WH)

  There is an upcoming release of Magic 6.45 that is supposed to have a
  greatly improved netlister.  Here is part of the annoucement:

  The AuE Magic release provides hierarchical SPICE and LSIM netlist
  extractors not available in previous Magic releases. Previously, a flat
  SPICE netlist could be obtained using a program called "ext2spice". AuE
  provides a hierarchical SPICE netlister which provides a robust set of
  SPICE parameters for every device, including transistor source/drain dif-
  fusion perimeters and areas. The extractor has also been modified to
  correctly account for the shared S/D regions on stacked devices.

  The AuE extractor supports LSIM netlists, an Hspice compatible netlist,
  and a SpiceIIG compatible netlist. The SpiceIIG format uses node numbers
  instead of node names. The AuE SPICE extractor also recognizes bipolar
  junction transistors (BJTs) in several configurations. The previous Magic
  netlist extractor does not recognize BJT devices in any form.

  Spice listing from magic with MESFETs.

  (from Jen-I Pi <[e-mail]>)

  We have a revised version (of sim2spice) that goes with version6. It is
  available from our anonymous FTP host "venera.isi.edu" (128.9.0.32) under
  the pub/mosis/magic directory. The file you need is "gaas_extract.tar.Z".

  Assuming file inv.ext exist, the procedure for using 'sim2spice' is

      ext2sim inv
      sim2spice inv.sim

  Here's the resulting SPICE decks for SPICE3e...

          SPICE 3 Deck created from inv.sim, tech=edgaas
          *
          z2 3 4 2 efet1.2 2.8
          C3 3 0    0.485F
          C4 4 0    1.062F
          z1 1 4 3 dfet1.2 2.8
          *

  A new capacitance rule has been added to the base Magic extractor to
  facilitate the extraction of accurate dielectric capacitances. The previ-
  ous verion of Magic did not handle coupling capacitances correctly and
  frequently inserted a substrate capacitor in addition to the correctly
  extracted coupling capacitor.

  The AuE Magic release also includes an updated and enhanced technology
  file.  Modifications include fixes to several MOSIS DRC rules which were
  previously improperly checked, modifications to the CIF writer to resolve
  software bugs, and updated capacitance and resistance values in the
  extraction sections of the tech file. Special extraction sections for
  more commonly used processes have also been added.

  For information on how to order this version of Magic send an E-mail
  request to [e-mail] or send your request in writing to the address
  given below. We will start filling orders in mid October.

4: Tips and tricks for magic (Version 6.3)

  Searching for nets:

  Yes, magic does actually let you search for node names.  Use :specialopen
  netlist.  Then click on the box underneath label, you will be prompted
  for the name of the label you want to search for.  Enter the name, and
  then press enter twice.  Click on show, and then find, magic will then
  highlight the net.

  Bulk node extraction:

  Problems with getting the bulk node to extract correctly?  Try labeling
  the well with the node name that it is connected to.

  Painting Wells:

  Supposedly :cif in magic will automatically paint in the wells correctly.
  However this is not always the case.  If you are using mosis 2u technol-
  ogy, and your wells are getting strange notches in them, you might try
  changing the grow 300 shrink 300 lines in your lambda=1.0(pwell) and
  lambda=1.0(nwell) cif sections of your tech file to grow 450 shrink 450.
  (Remember you can use :cif see CWN to see nwell, if :cifostyle is nwell,
  or :cif see CWP to see pwell if its pwell technology to preview what will
  be done with the well.  You may use :feedback clear to erase what it
  shows you.)

  Magic notes available from gatekeeper.dec.com (16.1.0.2):

  (Located in pub/DEC/magic)

  Magic note.1 - 9/14/90 - ANNOUNCEMENT:  Magic V6 is ready
  Magic note.2 - 9/19/90 - DOC:  Doc changes (fixed in releases after 9/20/90)
  Magic note.3 - 9/19/90 - GRAPHICS:  Mode problem (fixed 9/20/90)
  Magic note.4 - 9/19/90 - HPUX:  rindex macro for HPUX 7.0 and later
  Magic note.5 - 9/19/90 - GCC:  "gcc" with magic, one user's experience
  Magic note.6 - 9/19/90 - FTP:  Public FTP area for Magic notes
  Magic note.7 - 9/20/90 - RSIM:  Compiling rsim, one user's suggestions & hints
  Magic note.8 - 9/26/90 - GENERAL:  Magic tries to open bogus directories
  Magic note.9 - 9/26/90 - GRAPHICS:  Mods to X11Helper
  Magic note.10 - 10/5/90 - DOS:  Magic V4 for DOS and OS/2
  Magic note.11 - 10/11/90 - GENERAL:  reducing memory usage by 600k
  Magic note.12 - 12/19/90 - EXT2xxx:  fixes bogus resistances
  Magic note.13 - 12/19/90 - EXTRESIS:  fixed bug in resis that caused coredump.
  Magic note.14 - 12/19/90 - EXTRESIS:  new version of scmos.tech for extresis
  Magic note.15 - 12/19/90 - TECH:  documentation for contact line in tech file
  Magic note.16 - 12/19/90 - EXTRACT:  bug fix to transistor attributes
  Magic note.17 - 5/13/91 - CALMA:  Incorrect arrays in calma output
  Magic note.18 - 5/14/91 - CALMA:  Extension to calma input
  Magic note.19 - 6/28/91 - IRSIM:  Some .prm files for IRSIM
  Magic note.20 - 7/18/91 - EXTRESIS:  fixes for Magic's extresis command
  Magic note.21 - 2/7/92 - FAQ:  Frequently asked questions
  Magic note.22 - 11/6/91 - CALMA:  how to write a calma tape
  Magic note.23 - 11/4/91 - EXT2xxx:  fix for incorrect resistor extraction
  Magic note.24 - 11/8/91 - EXTRESIS:  fix 0-ohm resistors
  Magic note.25 - 11/15/91 - NEXT:  porting magic to the NeXT machine
  Magic note.26 - 11/21/91 - IRSIM:  fix for hanging :decay command
  Magic note.27 - 12/17/91 - RESIS:  fix for "Attempt to remove node ..." error
  Magic note.28 - 1/28/92 - MAGIC:  anonymous FTP now available
  Magic note.29 - 3/27/92 - PLOT:  support for Versatec 2700
  Magic note.30 - 4/8/92 - PATHS:  Have the ":source" command follow a path
  Magic note.31 - 4/10/92 - MPACK:  Mpack now works with Magic 6.3
  Magic note.32 - 3/13/92 - AED:  Using AED displays with Magic 6.3
  Magic note.33 - 3/13/92 - OPENWINDOWS:  Compilation for OpenWindows/X11
  Magic note.34 - 2/14/92 - OPENWINDOWS:  fix mouse problem

5: What can I use to do good plots from magic/CIF?

  (Thanks to Douglas Yarrington <[e-mail]> and Harry
  Langenbacher <[e-mail]>, for feedback here.)

  CIF:

  CIF stands for CalTech Intermediate Form. It's a graphics language which
  can be used to describe integrated circuit layouts.

  cif2ps  version 2 (Gordon W. Ross, MITRE):

  A much better version of cif2ps, extending the code of cif2ps (Marc
  Lesure, Arizona State University) and cifp (Arthur Simoneau, Aerospace
  Corp).  It features command line options for depth and formatting.  Can
  extend one plot over several pages (up to 5 by 5, or 25 pages). By
  default, uses a mixture of postscript gray fill and cross-hatching.
  Options include rotating the image, selecting the hierarchy depth to
  plot, and plotting style customization.  Plots are in B/W only.

  It was posted to comp.sources.misc, and is available by ftp from
  uunet.uu.net(192.48.96.2) as: comp.sources.misc/volume8/cif2ps.Z.

  cifplot:

  Cifplot plots CIF format files on a screen, printer or plotter.  Cifplot
  reads the .cif file, generates a b/w or color raster dump, and sends it
  to the printer.  Plots can be scaled, clipped, or rotated.  Hierarchy
  depth is selectable, as well as the choice of colormap or fill pattern.
  An option exists which will compress raster data to reduce the required
  disk space.  For those plotting to a Versatec plotter, there is also a
  printer filter/driver available called vdmp.

  cifplot (m2c version, from [e-mail] <Rit Chiang>):

  The cifplot program from M2C is not in public domain.  However, we do
  provide P.D. CAD tools to university for a fee of $2500/year to cover our
  cost on distribution, telephone hotline support, documentation and
  tutorials, etc., under our CUME (Clearinghouse for Undergraduate
  Microelectronics Education) program.  This program, in the past, was sub-
  sidized by NSF.

  The cifplot program was modified by M2C to support plotting for B&W
  PostScript and color PostScript printers, besides the versatec plotters.
  We also provide plotting services for people who sent us a cif file.  The
  cost is $20/per 24" color versatec plot for University and $50 for oth-
  ers.

  For more information on the CUME program or the plotting service, please
  send e-mail to [e-mail].

  oct2ps (available as part of the octtools distribution):

  It is possible to convert your .mag file to octtools, and then you may
  use oct2ps to print it.

  Both cif2ps and oct2ps work well for conversion to postscript.  They do
  look slightly different, so pick your favorite.  Note that cif2ps can be
  converted to adobe encapsulated postscript easily by adding a bounding
  box comment.  oct2ps does convert to color postscript, which can be a
  plus for those of you with color postscript printers.

  Flea:

  Flea ([F]un [L]oveable [E]ngineering [A]rtist) is a program used to plot
  magic and cif design files to various output devices. Parameters are
  passed to flea through the flags and flag data or through .flearc files
  and tech files.  Supports: HP7580 plotter, HP7550 hpgl file output,
  HP7550 plotter lpr output, Postscript file output, Laser Writer lpr out-
  put, Versatec versaplot random output.  Options include: Does line draw-
  ings with crosshatching for postscript, versatec, and hp plotters.  Many
  options (depth, label depth, scale, path, format...)

  Available by ftp from zeus.ee.msstate.edu in pub/flea.tar.Z.

  pplot:

  Can output color PostScript from CIF files. The source is available from:
  tesla.ee.cornell.edu in /pub/cad/pplot.tar.Z. It only generates PS files
  (including color PS), and there's no support for EPS files.  It is lim-
  ited in its support of cif commands.  (Wire, roundflash, and delete are
  not supported.)  It only supports manhattan geometry (Polygons and rota-
  tions may only be in 90 degree multiples.)

  vic:

  Part of the U. of Washington's Northwest Lab, for Integrated Systems Cad
  Tool Release (previously UW/NW VLSI Consortium).  Does postscript and HP
  pen plotters.  Only available as part of the package.

  CIF/Magic -> EPS -> groff/latex

  Currently no prgram here directly generates EPS files.  It is possible to
  add an EPS bounding box (%% BoundingBox: l t b r) to the output from
  these programs to get an EPS file.  Alternatively, ps2eps or ps2epsf may
  be used.

6: What tools are used to layout verification?

  Gemini:

  This is an excellent program that was done by Carl Ebeling.  There is a
  new version that is currently in beta.  This version supports serveral
  different netlist formats.  Devices with any number of terminals are sup-
  ported.  (This could be suitable for use at digital block level LVS, for
  example.)  LVS of mosfet w/l and capacitor values is supported as well.

  Contact:

          Carl Ebeling
          Computer Science Department, FR-35
          University of Washington
          Seattle, WA  98195
          [e-mail]

  Tanner LVS:

  This is a relatively inexpensive commercial product, see the section on
  Tanner tools.

  Wellchecker:

  (from MUG) ftp venera.isi.edu (128.9.0.32)

  netcmp:

  Part of the caltech tools (see the "Caltech VLSI CAD Tools" section)

7: EDIF data exchange format.

  (From Nigel Whitaker <[e-mail]>)

  EDIF Version 3 0 0 was announed/released at the Design Automation Confer-
  ence (DAC) at Dallas, Texas, 16/6/93.

  New Reference Manuals and EXPRESS information models for this new version
  of EDIF are available from the EIA:

  Electronic Industries Association Standard Sales Department (Attn:
  Cecelia Fleming) 2001 Pennsylvania Avenue, N.W.  Washington D.C. 20006,
  USA

  An electronic copy of the BNF, together with other EDIF related informa-
  tion such as tests files and EDIF documents can be obtained by anonymous
  ftp from edif.cs.man.ac.uk in subdirectories of /pub/edif.

  An ftpmail server is provided for those without ftp access.  Send an
  empty email message to: [e-mail] ; a message describing the
  commands which can be used in further email messages to retreive files
  will be sent to you.

  An electonic mailing list is available to people interested in EDIF and
  for EDIF developers/programmers.  Send email to edif-users-
  [e-mail] to be added.

  The EDIF Technical Centre (based at the University of Manchester and
  funded by the CEC as part of ESPRIT 2072 -- ECIP) can be contacted by the
  following means:

  EDIF Technical Centre, Depeartment of Computer Science University of Man-
  chester, Manchester, M13 9PL, UK

  Tel: [phone] FAX: [phone] e-mail: edif-
  [e-mail]

8: What layout examples are available?

  From MUG:

  Analog neural network library of cells, 66-bit Manchester carry-skip
  adder, static ram fabricated at 2-micron, an analog op amp, ftp
  venera.isi.edu (128.9.0.32) Located in pub/mug.

9: How can I get my lsi design fabbed and how much will it cost?

  See section on mosis fabrication services as well.

  (From [e-mail] <Rit Chiang>) M2C can also provide low-cost, low-
  volume prototyping fab services.  The current technology available to the
  public is the  2um NWell single-poly double-metal process.

  For pricing information and fab schedule, please send e-mail to
  [e-mail].

  Unfortunately, the fab line is currently inactive.  We have no informa-
  tion as to when the fab will be back up.

  (From MUG 20 George Lewicki of Orbit Semiconductor)

  Orbit Semiconductor operates an integrated circuit prototyping service
  that accepts designs each week for all of its processes.  The service is
  available to both U.S. and non-U.S. designers. In- quiries about the
  FORESIGHT prototyping service should be ad- dressed to George Lewicki.
  Designs can now be submitted directly via email.

              Orbit Semiconductor, Inc.
              1215 Bordeaux Drive
              Sunnyvale, CA 94089
              TEL: [phone]
              FAX: [phone]
              Email: [e-mail]

  (Contributed by Don Bouldin of the University of Tennessee)

  Recently, I contacted several foundries to determine  which  com- panies
  are  interested  in fabricating small to moderate lots of wafers for cus-
  tom CMOS designs.  I believe many of the readers of this  column are
  designers who wish to have fabricated only 1,000 to 20,000 parts per
  year.  There are currently several  prototyp- ing  services  (e.g. MOSIS
  and Orbit) that can produce fewer than 100 parts for about $100 each and
  there are  also  several  foun- dries  which  are willing to produce
  100,000 custom parts for $5- $20 each (depending on the die size and
  yield).  My  purpose  was to  identify  those companies filling the large
  gap between these two services.

  The prices in the table below are a result of averaging the  data sup-
  plied by four foundries.  The raw data varied by more than +/- 40% so the
  information should be used only in the early stages of budgetary  plan-
  ning.   Once  the design specifications are fairly well known, the
  designer should contact one or more foundries  to obtain  specific
  budgetary  quotes.  As the design nears comple- tion, binding quotes can
  then be obtained.

  The following assumptions were made by the foundries:

  All designs will require custom CMOS wafer  fabrication  using  a
  double-metal, single-poly process with a feature size between 2.0 and 1.2
  microns.  The designs may contain some  analog  circuitry and  some  RAM
  so the yield has been calculated pessimistically.  The dies will be pack-
  aged and tested at 1  MHz  using  a  Sentry- type digital tester for 5-10
  seconds per part.  The customer will furnish the test vectors.

          Piece Price includes Wafer Fabrication+Die Packaging+Part Testing
          Size        Package                      Quantity

                                 |1,000 | 5,000 | 10,000 | 20,000  |100,000
          -----------------------------------------------------------------
          2 mm x 2 mm; 84 PLCC:  | $ 27 | $  6  |  $  5  |  $  4   | $  3 |
          5 mm x 5 mm; 84 PLCC:  | $ 31 | $ 12  |  $  8  |  $  7   | $  6 |
          5 mm x 5 mm; 132 PGA:  | $ 49 | $ 30  |  $ 25  |  $ 22   | $ 18 |
          7 mm x 7 mm; 132 PGA:  | $ 65 | $ 44  |  $ 36  |  $ 31   | $ 27 |

          Lithography charges:  $ 20,000 - $ 40,000
          Preferred Formats:  GDS-II or  CIF Tapes
          Additional charges for Second-Poly:  $ 5,000

  (This is from MUG 19, there is also a list of foundries that these prices
  were derived from.  In the interested of saving space, I have ommitted
  the list.  The list is available from MUG's ftp site included in MUG
  newsletter #19.)

10: Mosis fabrication services.

  (From Mosis) Information is available from mosis for pricing and fab
  schedules through an automatic email system:

  Mail to [e-mail] with the message body as follows:

          REQUEST: INFORMATION
          TOPIC: TOPICS
          REQUEST: END

  for general information and a list of available topics.

  If you need to contact a person at mosis, you may mail to [e-mail]
  with REQUEST: ATTENTION.

  Also anonymous ftp is available. ftp to ftp.mosis.edu.  This is a dupli-
  cation of all files that are available from the mail server.

  (From MUG 20 Contributed by Don Bouldin of the University of Tennessee)

  Multi-project fabrication of BICMOS designs are already available to
  European universities via CMP and to Canadian universities via the Cana-
  dian Microelectronic Corporation.  However, in the United States, the
  demand for BiCMOS fabrication via MOSIS has not been considered signifi-
  cant.  MOSIS is currently planning to start offering 0.5-micron BiCMOS
  during the first quarter of 1994. This will have a core voltage operation
  of 3.3v and a clock frequency in the range of 220-250Mhz.  MOSIS is
  interested in seeing if a larger demand exists in the community than
  expressed so far.

  If you would like to have BiCMOS available before 1994, please send a
  short note to [e-mail] (with a copy to [e-mail])
  using the following format.

               REQUEST:  ATTENTION
                          .
                          .
                   your message goes here
                          .
                          .
               REQUEST: END

  (From MUG 20 and Chris Donham of the University of Pennsylvania)

  Support for mosis technologies under Cadence Analog Artist 2.4 is avail-
  able as is from University of Pennsylvania.  This includes DRC, LVS, EXT,
  and a beginner's guide.  Currently they are working on support for Opus
  4.2.  The files supporting Artist 2.4 are currently available via
  anonymous FTP.  Penn is not affiliated with MOSIS, except as a satisfied
  customer, and as a result, NO WARRANTY IS EXPRESSED OR IMPLIED WITH
  REGARDS TO THE FILES, OR THEIR FITNESS FOR ANY USE.  Use the files at
  your own risk.  To obtain the files, FTP to axon.ee.upenn.edu
  (130.91.6.208), using the name "anonymous" and your mailing address as
  the password.  The files are in the "pub" directory.

  Penn is in the process of switching from Artist 2.4 to Opus 4.2.  The
  manual is being rewritten, and the support files are being updated.
  Technology files supporting DRC, Extract, and Compare are currently in
  beta-test.  If problems or bugs are detected, please send email to
  "[e-mail]".

11: Archive sites for comp.lsi.cad and comp.lsi

  (None of these are comprehensive archives, rather, they have about 3
  postings each)

  comp.lsi.cad:
  cnam.cnam.fr in /pub/Archives/comp.archives/auto/comp.lsi.cad
  cs.dal.ca in /pub/comp.archives/comp.lsi.cad
  srawgw.sra.co.jp in /.a/sranha-bp/arch/arch/comp.archives/auto/comp.lsi.cad

12: Other newsgroups that relate to comp.lsi*

  alt.cad
  comp.cad.cadence
  comp.lang.verilog
  comp.lang.vhdl
  comp.sys.mentor
  sci.electronics

13: Simulation programs tips/tricks/bugs

  Berkeley spice:

  Pspice:

  Hspice:

  If your simulation won't converge for a given DC input, you can ramp the
  input and print the DC operating point and then set the nodes that way
  for future simulations.

  A number of documents are available for information on BSIM model parame-
  ters: (from Mark Johnson, as posted to comp.lsi <[e-mail]>)

  1. The very best written description I have seen is in a software manual.
     The good news is that this manual is free; the bad news is that you
     have to buy the multi-thousand-dollar program in order to get the free
     manual.  The program is HSPICE from Meta-Software Inc (Campbell,
     Calif., USA).  The HSPICE User's Manual, chapter 7, gives all the
     details you'd ever want to know regarding BSIM parameters.

  2. The second best description I have seen of BSIM is in, strangely
     enough, a manual for BSIM2 (!).  It is available from the University
     of California at Berkeley.  Telephone [phone] and they will
     give you instructions on how to buy the manual.  (They'll probably
     suggest that you might want to buy some software too).

             J.S. Duster, M.C. Jeng, P.K. Ko, and C. Hu, "Users
             Guide for the BSIM2 Parameter Extraction Program and
             the SPICE3 with BSIM Implementation"

  3. You can learn some things about BSIM parameters by reading about pro-
     grams which extract the parameters from measured data.  UC Berkeley
     offers several programs and manuals for this.  The one that I person-
     ally prefer is

             M.C. Jeng, B.J. Sheu, and P.K. Ko: "BSIM Parameter
             Extraction - Algorithms and User's Guide," Memo
             No. UCB/ERL M85/79, 7 October 1985.

  4. Next, look at Sheu's Ph.D. thesis.  He is the guy who combined the
     Bell Labs CSIM model with a bunch of other published equations, and
     formulated BSIM.  It's available from the same phone number.

             B.J. Sheu, "MOS Transistor Modelling and Characterization
             for Circuit Simulation", Memo No. UCB/ERL M85/85,
             26 October 1985

  5. The worst description (in +my+ opinion of course) is unfortunately in